1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for forming a semiconductor memory device, and more particularly to a circuit arrangement method that is suitable for use in a DDR SDRAM (double data rate synchronous DRAM).
2. Background of the Invention
FIG. 7 shows a block diagram of the write system of a SDR type SDRAM (single data rate synchronous DRAM), FIG. 7(a) being an example in which within a region in which data latch circuits 121, 122, . . . 12n are disposed between a second straight line 112 which is perpendicular to a first straight line 111 that passes over pads 101 through 10n and which also passes over the data pad 101, and a third straight line 113, which is parallel to the second straight line 112 and which also passes over the pad 10n, a plurality of data latch circuits 121 to 12n are distributed, which latch signals from the data pads, and FIG. 7(b) being an example in which a data latch group 210 comprising a plurality of data latch circuits is centrally located in a region that is surrounded by the second straight line 112 and the third straight line 113.
In the case of FIG. 7(b), because the wiring between the first stage and the data latch circuit is long, the power consumption and wiring area are large, the result being that the wiring method shown in FIG. 7(a) was used in SDR DRAMs of the past.
When designing a DDR SDRAM (double data rate synchronous DRAM), however, as shown in FIG. 8, if the same arrangement as shown in FIG. 7(a) is used, it becomes impossible to latch data, as shown by the data latch timing diagram of FIG. 9. This is because, whereas in the case of a SDR DRAM the timing of data latching is only at the rising edge of the clock signal, with a DDR DRAM because data is latched at both the rising and falling edges of the clock signal, so that there is double the number of operations as with an SDR DRAM, the data hold time is halved from what it was in the past, making the timing conditions more severe, so as to prevent latching of data.
The reasons that data cannot be latched have been demonstrated to be variation in time delay caused by differences in the length of wiring from the each of the data latch circuits 121 through 12n to the internal clock (CLK) signal generating circuit 130, and delay time skews between the internal clock delay time (tCLK delay) and the external clock, and between an internal data delay time (tDQ delay) and external data.
Accordingly, it is an object of the present invention, in view of the above-noted drawbacks in the related art, to provide a novel semiconductor memory device which improves on the above-noted problems, and which features interconnect and element regions of reduced size, thereby avoiding an increase in chip size, while being suitable for application as a DDR SDRAM. It is a further object of the present invention to provide a method of forming the above-noted semiconductor memory device.